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www.fairchildsemi.com rev. 1.0.2 10/25/00 features four user-selectable ?tering and transformation functions: triple dot product (3 x 3) matrix multiply cascadeable 9-tap systolic fir ?ter cascadeable 3 x 3-pixel image convolver cascadeable 4 x 2-pixel image convolver 50 mhz (20ns) pipelined throughput 12-bit input and output data, 10-bit coef?ients 6-bit cascade input and output ports in all ?ter modes onboard coef?ient storage, with three-cycle updating of all nine coef?ients applications image ?tering and manipulation video effects generation video standards conversion and encoding/decoding three-dimensional image manipulation medical image processing edge detection for object recognition fir ?tering for communications systems description the tmc2250a is a ?xible high-performance nine-multiplier array vlsi circuit which can execute a cascadeable 9-tap fir ?ter, a cascadeable 4 x 2 or 3 x 3-pixel image convolu- tion, or a 3 x 3 color space conversion. all con?urations offer throughput at up to the maximum guaranteed 50 mhz clock rate with 12-bit data and 10-bit coef?ients. all inputs and outputs are registered on the rising edges of the clock. the 3 x 3 matrix multiply or color conversion con?uration can perform video standard conversion (yiq or yuv to rgb, etc.) or three-dimensional perspective translation at real-time video rates. the 9-tap fir ?ter con?uration, useful in video, telecom- munications, and signal processing, features a 16-bit cascade input to allow construction of longer ?ters. the cascadeable 3 x 3 and 4 x 2-pixel image convolver func- tions allow the user to perform numerous image processing functions, including static ?ters and edge detectors. the 16-bit cascade input port facilitates two-chip 50 mhz cubic convo- lution (4 x 4-pixel kernel). the tmc2250a is fabricated in a sub-micron cmos process and operates at clock speeds of up to 50 mhz over the full commercial (0? to 70?) temperature and supply voltage ranges. it is available in 120-pin plastic pin grid array (ppga) packages, 120-lead ceramic pin grid array pack- age (cpga), 120-lead pqfp to ppga package (mpga) and 120-lead plastic quad flatpack (pqfp). all input and output signals are ttl compatible. tmc2250a matrix multiplier 12 x 10 bit, 50 mhz
product specification tmc2250a 2 rev. 1.0.2 10/25/00 functional description the tmc2250a is a nine-multiplier array with the internal bus structure and summing adders needed to implement a 3 x 3 matrix multiplier (triple dot product) a cascadeable 9-tap fir ?ter, a 3 x 3-pixel convolver, or a 4 x 2-pixel convolver all in one monolithic circuit. with a 50mhz guaranteed maximum clock rate, this device offers video and imaging system designers a single-chip solution to numerous common image and signal-processing problems. the three data input ports (a, b, c) accept 12-bit two's com- plement integer data, which is also the format for the output ports (x, y, z) in the matrix multiply mode (mode 00). in the ?ter con?urations (modes 01, 10, and 11) the cascade ports assume 12-bit integer, 4-bit fractional two's complement data on both input and output. the coef?ient input ports (ka, kb, kc) are always 10-bit two's complement fractional. table 1 details the bit weighting of the input and output data in all con?urations. operating modes the tmc2250a can implement four different digital ?ter architectures. upon selection of the desired function by the user (mode 1-0 ), the device recon?ures its internal data paths and input and output buses appropriately. the output ports (xc, yc and zc) are con?ured in all ?ter modes a 16-bit cascade in and cascade out ports so that multiple devices can be connected to build larger ?ters. these modes are described individually below. the i/o function con?u- rations for all four modes are shown in table 1. de?itions the calculations performed by the tmc2250a in each mode are also shown below, utilizing the following notation: a(1), b(5), c(2), casin(3) indicates the data word presented to that input port during the speci?d clock rising edge(x). applies to all input ports a 11-0 , b 11-0 , c 11-0 , and casin 15-0 . ka1(1), kb3(4) indicates coef?ient data stored in the speci?d one of the nine onboard coef?ient registers ka1 through kc3, as shown in the block diagram for that mode, input during or before the speci?d clock rising edge (x). x(1), y(4), z(6), casout (6) indicated data available at that output port t do after that speci?d clock rising edge (x). applies to all output ports x 11-0 , y 11-0 , z 11-0 , and casout 15-0 . numeric format table 2 shows the binary weightings of the input and output ports of the tmc2250a. although the internal sums of prod- ucts could grow to 23 bits, in the matrix multiply mode (mode 00) the outputs x, y and z are rounded to yield 12-bit integer words. thus the output format is identical to the input data format. in the ?ter con?urations (modes 01, 10, and 11) the cascade output is always half-lsb rounded to 16 bits, speci?ally 12 integer bits and 4 fractional guard bits, with no over?w "headroom". the user is of course free to half-lsb round the output word to any size less than 16 bits by forcing a 1 into the bit position of the cascade input immediately below the desired lsb. in all modes, bit weighting is easily adjusted if desired by applying the same scaling correction factor to both input and output data words. if the coef?ients are rescaled, the relative weightings of the casin and casout ports will differ accordingly. data over?w as shown in table 2, the tmc2250a's matched input and output data formats accommodate 0db (unity) gain. there- fore, the user must be aware of input conditions that could lead to numeric over?w. maximum input data and coef? cient word sizes must be taken into account with the speci? algorithm performed to ensure that no over?w occurs. table 1. data port formatting by mode mode inputs inputs/output outputs a 11-0 b 11-0 c 11-0 ka 9-0 kb 9-0 kc9-0 xc 11-0 yc 11-8 y 7-4 yc3-0 zc 11-0 00 a 11-0 b 11-0 c 11-0 ka 9-0 kb 9-0 kc9-0 x 11-0 y 11-8 y 7-4 y 3-0 z 11-0 01 a 11-0 b 11-0 nc ka 9-0 kb 9-0 kc9-0 casin 15-4 casin 3-0 nc casout 3-0 casout 15-4 10 a 11-0 b 11-0 c 11-0 ka 9-0 kb 9-0 kc9-0 casin 15-4 casin 3-0 nc casout 3-0 casout 15-4 11 a 11-0 b 11-0 nc ka 9-0 kb 9-0 kc9-0 casin 15-4 casin 3-0 nc casout 3-0 casout 15-4
tmc2250a product specification rev. 1.0.2 10/25/00 3 table 2. bit weightings for input and output data words note: a minus sign indicates a two? complement sign bit. bit weights 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 .2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 inputs all modes data a, b, c -i 11 i 10 i 9 i 8 i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 . coefficients ka, kb, kc -k 9 .k 8 k 7 k 6 k 5 k 4 k 3 k 2 k 1 k 0 modes 01, 10, 11 casin -ci 15 ci 14 ci 13 ci 12 ci 11 ci 10 ci 9 ci 8 ci 7 ci 6 ci 5 ci 4 .ci 3 ci 2 ci 1 ci 0 internal sum x 20 x 19 x 18 x 17 x 16 x 15 x 14 x 13 x 12 x 11 x 10 x 9 .x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 outputs mode 00 x, y, z -o 11 o 10 o 9 o 8 o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 . modes 01, 10, 11 casout - co 15 co 1 4 co 1 3 co 1 2 co 1 1 co 1 0 co 9 co 8 co 7 co 6 co 5 co 4 .co 3 co 2 co 1 co 0
product specification tmc2250a 4 rev. 1.0.2 10/25/00 pin assignments 120 pin plastic quad flat pack (mqfp), ke package xc 6 xc 5 xc 4 xc 3 xc 2 xc 1 xc 0 gnd yc 11 yc 10 yc 9 v dd yc 8 y 7 y 6 gnd y 5 y 4 yc 0 v dd yc 1 yc 2 yc 3 gnd zc 0 zc 1 zc 2 zc 3 zc 4 zc 5 1 30 120 91 31 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 61 zc 6 zc 7 zc 8 gnd zc 9 zc 10 zc 11 kc 0 kc 1 kc 2 kc 3 gnd kc 4 kc 5 kc 6 v dd kc 7 kc 8 kc 9 kb 0 kb 1 kb 2 kb 3 kb 4 kb 5 kb 6 kb 7 kb 8 kb 9 ka 0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 pin name pin name ka 1 ka 2 ka 3 ka 4 ka 5 ka 6 ka 7 ka 8 ka 9 cwe 1 cwe 0 gnd a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 b 0 b 1 b 2 clk b 3 b 4 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 b 5 b 6 b 7 b 8 b 9 b 10 b 11 c 0 c 1 c 2 c 3 v dd c 4 c 5 c 6 gnd c 7 c 8 c 9 c 10 c 11 mode 1 mode 0 gnd xc 11 xc 10 xc 9 v dd xc 8 xc 7 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 pin name pin name
tmc2250a product specification rev. 1.0.2 10/25/00 5 pin assignments (continued) 120 pin plastic pin grid array, h5 package and 120 pin ceramic pin grid array, g1 package and 120 pin plastic quad flatpack to 120-pin pin grid array (mpga) b adefghjklmn c 1 2 3 4 5 6 7 8 9 10 11 12 13 top view cavity up key xc 7 xc 9 xc 10 mode 0 c 11 c 8 c 7 c 5 c 3 c 1 b 10 b 7 b 4 xc 4 xc 5 xc 8 xc 11 mode 1 c 9 c 6 c 4 c 2 b 11 b 9 b 6 b 2 xc 1 xc 2 xc 6 v dd a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 c1 c2 c3 c4 gnd c 10 gnd v dd c 0 b 8 b 5 b 3 b 1 yc 11 xc 0 xc 0 clk b 0 a 10 yc 9 yc 10 gnd a 11 a 9 a 8 y 7 yc 8 v dd a 7 a 6 a 5 y 5 y 6 gnd c5 c6 c7 c8 c9 c10 c11 c12 c13 d1 d2 d3 d11 d12 d13 e1 e2 e3 e11 e12 e13 f1 f2 f3 f11 f12 f13 g1 g2 g3 pin name pin name a 3 a 2 a 3 y 4 yc 0 v dd gnd a 0 a 1 yc 1 yc 2 gnd ka 8 cwe 1 cwe 0 yc 3 zc 0 zc 3 ka 4 ka 7 ka 9 zc 1 zc 4 zc 6 gnd kc 0 gnd v dd kb 0 kb 4 g11 g12 g13 h1 h2 h3 h11 h12 h13 j1 j2 j3 j11 j12 j13 k1 k2 k3 k11 k12 k13 l1 l2 l3 l4 l5 l6 l7 l8 l9 kb 8 ka 1 ka 5 ka 6 zc 2 zc 7 zc 9 zc 11 kc 2 kc 4 kc 6 kc 9 kb 2 kb 5 kb 9 ka 2 ka 3 zc 5 zc 8 zc 10 kc 1 kc 3 kc 5 kc 7 kc 8 kb 1 kb 3 kb 6 kb 7 ka 0 l10 l11 l12 l13 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 pin name pin name
product specification tmc2250a 6 rev. 1.0.2 10/25/00 pin descriptions pin name pin number function pin description cpga/ppga/ mpga mqfp power v dd f3, h3, l7, c8, c4 12, 20, 46, 102, 118 supply voltage the tmc2250a operates from a single +5v supply. all pins must be connected. gnd e3, g3, j3, l4, l6, h11, c7, c5 8, 16, 24, 34, 42, 72, 106, 114 ground the tmc2250a operates from a single +5v supply. all pins must be connected. clock clk d11 88 system clock the tmc2250a operates from a single system clock input. all timing specifications are referenced to the rising edge of clock. controls mode 1,0 b4, a4 112, 113 mode control the tmc2250a will switch to the configuration selected by the user (as shown in table 3) on the next clock. this registered control is usually static; however, should the user wish to switch between modes, the internal pipeline latencies of the device must be taken into account. valid data will not be available at the outputs in the new configuration until enough clocks in the new mode have passed to flush the internal registers. cwe 1,0 j12, j13 70, 71 coefficient write enable data presented to the coefficient input ports (ka, kb, and kc) will update three of the internal coefficient storage registers, as indicated by the simultaneous coefficient write enable select, on the next clock. see table 4 and the functional block diagram. input/output a 11-0 e11, d13, e12, e13, f11, f12, f13, g13, g11, g12, h13, h12 84, 83, 82, 81, 80, 79, 78, 77, 76, 75, 74, 73 data input a data presented to the 12-bit registered data input ports a, b, and c are latched into the multiplier input registers for the currently selected configuration (table 3). in all modes except mode 00, new data are internally right-shifted to the next filter tap on each rising edge of clk. b 11-0 b10, a11, b11, c10, a12, b12, c11, a13, c12, b13, c13, d12 97, 96, 95, 94, 93, 92, 91, 90, 89, 87, 86, 85 data input b c 11-0 a5, c6, b6, a6, a7, b7, a8, b8, a9, b9, a10, c9 111, 110, 109, 108, 107, 105, 104, 103, 101, 100, 99, 98 data input c
tmc2250a product specification rev. 1.0.2 10/25/00 7 notes: 1. the output ports x, y, z and casout, and input port casin are internally reconfigured by the device as required for each mode of the device. the multiple-function pins have names which are combinations of these titles, as appropriate. 2. the output drivers on pins xc 11-0 and yc 11-8 are not necessarily disabled until after the first rising edge of clk following power-up. if these pins are to be tied to other output drivers, to each other, or to ground or v dd , the user should ensure that a clock pulse arrives within a few seconds of power-up, to avoid bus contention. ka 9-0 k13, j11, k12, l13, l12, k11, m13, m12, l11, n13 69, 68, 67, 66, 65, 64, 63, 62, 61, 60 coefficient input a1, a2, a3 data presented to the 10-bit registered coefficient input ports ka, kb and kc are latched three at a time into the internal coefficient storage register set indicated by the coefficient write enable cwe 1,0 on the next clock, as shown in table 4. kb 9-0 m11, l10, n12, n11, m10, l9, n10, m9, n9, l8 59, 58, 57, 56, 55, 54, 53, 52, 51, 50 coefficient input b1, b2, b3 kc 9-0 m8, n8, n7, m7, n6, m6, n5, m5, n4, l5 49, 48, 47, 45, 44, 43, 41, 40, 39, 38 coefficient input b1, b2, b3 xc 11-0 b4, a3, a2, b3, a1, c3, b2, b1, d3, c2, c1, d2 115, 116, 117, 119, 120, 1, 2, 3, 4, 5, 6, 7 casin 15-4 / output x in all modes except mode 00, the x port and four bits of the y output port are reconfigured as the 16-bit registered cascade input port casin 15-0 . data presented to this input will be added to the weighted sums of the data words which were presented to the input ports (a, b and c). in the matrix multiply mode, data are available at the 12-bit registered output ports x, y and z t do after every clock. these ports are reconfigured in the filtering modes as 16-bit cascade input and output ports.casout 15-0 in all modes except mode 00, the z port and four bits of the y output port are reconfigured as the 16-bit registered cascade output port casout 15-0 . yc 11-8 d1, e2, e1, f2 9, 10, 11, 13 casin 3-0 / output y 11-0 y 7-4 f1, g2, g1, h1 14, 15, 17, 18 output 7-4 only yc 3-0 k1, j2, j1, h2 23, 22, 21, 19 casout 3-0 / output y 3-0 zc 11-0 m4, n3, m3, n2, m2, l3, n1, l2, k3, m1, l1, k2 37, 36, 35, 33, 32, 31, 30, 29, 28, 27, 26, 25 casout 15-4 / output z 11-0 pin descriptions (continued) pin name pin number function pin description cpga/ppga/ mpga mqfp table 3. con guration mode word table 4. coef cient write enable word mode 1,0 con guration mode 00 3 x 3 matrix multiply 01 9-tap one dimensional fir 10 3 x 3 -pixel convolver 11 4 x 2 -pixel convolver cwe 1,0 coef cient set selected 00 hold all registers 01 update ka1, kb1, kc1 10 update ka2, kb2, kc2 11 update ka3, kb3, kc3
product specification tmc2250a 8 rev. 1.0.2 10/25/00 table 5. coef cient input ports 3 x 3 matrix multiplier (mode 00) this mode utilizes all six input and output ports in the basic con?uration to realize a "triple dot product", in which each output is the sum of all three input words in that column multiplied by the appropriate stored coef?ients. the three corresponding sums of products are available at the outputs ?e clock cycles after the input data are latched, and three new data words half-lsb rounded to 12 bits are then avail- able every clock cycle. x(5)=a(1)ka1(1)+b(1)kb1(1)+c(1)kc1(1) y(5)=a(1)ka2(1)+b(1)kb2(1)+c(1)kc2(1) z(5)=a(1)ka3(1)+b(1)kb3(1)+c(1)kc3(1) input port registers available ka ka1, ka2, ka3 kb kb1, kb2, kb3 kc kc1, kc2, kc3 figure 1. 3 x 3 matrix multiplier impulse response (mode 00) 1 01 10 11 0 0 1.0 0 00 00 ka 1 + kb 1 + kc 1 ka 2 + kb 2 + kc 2 ka 3 + kb 3 + kc 3 k_1 k_2 k_3 00 clk cwe ka, kb, kc data in a, b, c mode control x out y out z out 2345678
tmc2250a product specification rev. 1.0.2 10/25/00 9 figure 2. 3 x 3 matrix multiplier configuration (mode 00) 12 z 12 (msb) 5 rnd 12 y 12 (msb) 5 rnd ka1 a 12 ka 10 b 12 kb 10 c 12 kc 10 12 21 10 10 1 ka2 12 21 10 10 3 4 ka3 12 21 10 10 3 4 kb1 12 21 10 10 1 3 4 kb2 12 21 10 10 3 4 kb3 12 21 10 10 3 4 kc1 12 21 10 10 1 12 x 12 (msb) 3 4 kc2 12 21 10 10 3 4 kc3 12 21 10 10 3 4 3 4 5 rnd 222 222 222
product specification tmc2250a 10 rev. 1.0.2 10/25/00 9-tap fir filter mode (01) the architecture for this con?uration is shown in figure 4. the user loads the desired coef?ient set, presents input data to ports a and b simultaneously (most applications will wire the a and b inputs together), and receives the resulting 9- sample response, half-lsb rounded to 16 bits, 5 to 13 clock cycles later. a new output data word is available every clock cycle. the ?ure shows that the input data are automatically right- shifted by one position through the row of multiplier input registers on every clock in anticipation of a new input data word. casout(13) = a(9)ka3(9)+a(8)ka2(8)+a(7)ka1(7) +b(6)kb3(9)+b(5)kb2(8)+b(4)kb1(7) +b(3)kc3(9)+b(2)kc2(8)+b(1)kc1(7) +casin(10) latency: impulse in to center of 9-tap response =9 registers. cascade in to cascade out=4 registers. figure 3. 9-tap fir filter impulse response (mode 01) clk 1 01 10 11 1.0 01 q 13 q 13 kc 1 kc 2 kc 3 kb 1 kb 2 kb 3 ka 1 ka 2 ka 3 k_1 k_2 k_3 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 14 cwe ka, kb, kc data in a, b mode control casin casout
tmc2250a product specification rev. 1.0.2 10/25/00 11 figure 4. 9-tap fir filter configuration (mode 01) 16 z = casout (0 - 15) 16 (msb) 4 - 13 ka1 a 12 ka 10 b 12 kb 10 c kc casin (0 - 15) 10 16 16 (msb) 10000 half lsb rounding 12 21 10 10 1 ka2 12 21 10 10 3 4 ka3 12 21 10 10 3 4 kb1 12 21 10 10 1 2 3 4 6 7 kb2 12 21 10 10 6 7 kb3 12 21 10 10 6 7 kc1 12 21 21 21 21 21 21 10 10 9 10 kc2 12 21 10 10 9 10 kc3 12 21 10 10 9 10 3 4 5 2, 5, 8, 11 3, 5, 6 8, 9, 11, 12 888 5 5 6 55 222 7
product specification tmc2250a 12 rev. 1.0.2 10/25/00 3 x 3 pixel convolver (mode 10) this ?ter con?uration accepts a 3 pixel-square neighbor- hood, side-loaded three pixels at a time through input ports a, b and c, and multiplies the 9 most recent pixel values by the coef?ient set currently stored in the registers. these products are summed with the data presented to the cascade input, and a new 3-cycle impulse response, rounded to 16 bits, is available at the output port 5 to 7 clocks later, with a new output available on every clock cycle. the input pixel data are automatically shifted one location to the right through the three rows of multiplier input registers on every clock in anticipation of three new input data words, effectively sliding the convolutional window over one col- umn in an image plane. casout(7)= a(3)ka3(3)+a(2)ka2(2)+a(1)ka1(1) +b(3)kb3(3)+b(2)kb2(2)+b(1)kb1(1) +c(3)kc3(3)+c(2)kc2(2)+c(1)kc1(1) +casin(4) latency: impulse in to center of 3-tap response = 6 registers. cascade in to cascade out=4 registers. figure 5. 3 x 3-pixel convolver impulse response (mode 10) clk 1 01 10 11 1.0 01 q 17 q 7 k 1 k 2 k 3 k j = ka j + kb j + kc j k_1 k_2 k_3 234567891011 cwe ka, kb, kc data in a, b, c mode 10 casin casout
tmc2250a product specification rev. 1.0.2 10/25/00 13 figure 6. 3 x 3-pixel convolver configuration (mode 10) 16 z = casout (0 - 15) 16 (msb) 4 - 7 ka1 a 12 ka 10 b 12 kb 10 kc casin (0 - 15) 10 16 16 (msb) 10000 half lsb rounding 12 21 10 10 1 ka2 12 21 10 10 3 4 ka3 12 21 10 10 3 4 kb1 12 21 10 10 1 3 4 kb2 12 21 10 10 3 4 kb3 12 21 10 10 3 4 kc1 12 21 21 21 21 21 21 10 10 3 4 kc2 12 21 10 10 3 4 kc3 12 21 10 10 3 4 3 4 5 2, 5 3, 5, 6 222 222 222 c 12 1 1
product specification tmc2250a 14 rev. 1.0.2 10/25/00 4 x 2-pixel cascadeable convolver (mode 11) similar to mode 10, the 4 x 2 -pixel convolver allows the use to perform full-speed cubic convolution with only two tmc2250a devices and the tmc2111a pipeline delay register to synchronize the cascade ports (see the applica- tions discussion section). pixel data are side-loaded into ports a and b, multiplied by the onboard coef?ients, summed with the cascade input, and half-lsb rounded to 16 bits. the four-cycle impulse response emerges at the cascade output port 5 to 8 clock cycles later. a new output word is available on every clock cycle. note that multiplier kc2 is not used in this mode and that its stored coef?ient is ignored. as shown below, the column of input pixel data is automati- cally shifted one location to the right through the two rows of multiplier input registers on every clock in anticipation of two new input data words, effectively sliding the convolu- tional window over one column in an image plane. casout(8)= a(4)ka3(4)+a(3)ka2(3)+a(2)ka1(2) +a(1)kb3(4)+b(4)kb3(4)+b(3)kb2(3) +b(2)kb1(2)+b(1)kc1(2)+casin(5) figure 7. 4 x 2-pixel convolver impulse response (mode 11) clk 1 01 10 11 00 1.0 11 q 8 q 8 ka 2 + kb 2 kc 1 + kc 3 ka 3 + kb 3 ka 1 + kb 1 k_1 k_2 k_3 234567891011 cwe ka, kb, kc data in a, b mode casin casout
tmc2250a product specification rev. 1.0.2 10/25/00 15 figure 8. 4 x 2-pixel convolver configuration (mode 11) 16 z = casout (0 - 15) 16 (msb) 4 - 8 ka1 a 12 ka 10 b 12 kb 10 c kc casin (0 - 15) 10 16 16 (msb) 10000 half lsb rounding 12 21 10 10 1 ka2 12 21 10 10 3 4 ka3 12 21 10 10 3 4 kb1 12 21 10 10 1 3 4 kb2 12 21 10 10 3 4 kb3 12 21 10 10 3 4 kc1 12 21 21 21 21 21 21 10 10 4 5 kc2 12 21 10 10 kc3 12 21 10 10 6 7 3 4 5 3 0 5 222 222 1 2 3 4 2, 5 6 3, 5, 6, 7 2 2
product specification tmc2250a 16 rev. 1.0.2 10/25/00 figure 9. input/output timing diagram t cy t s t h t ho t d previous new t pwl t pwh 1 clk cwe ka, kb, kc x, y, z casout 2345 figure 10. equivalent digital input circuit figure 11. equivalent digital output circuit digital input v dd p n gnd v dd p n gnd digital output absolute maximum ratings (beyond which the device may be damaged)1 notes: 1. functional operation under any of these conditions is not implied. performance and reliability are guaranteed only if operating conditions are not exceeded. 2. applied voltage must be current limited to specified range. 3. forcing voltage must be limited to specified range. 4. current is specified as conventional current flowing into the device. parameter min typ max unit supply voltage -0.5 7.0 v input voltage -0.5 v dd + 0.5 v applied voltage 2 -0.5 v dd + 0.5 v externally forced current 3,4 -3.0 6.0 ma short circuit duration (single output in high state to ground) 1 sec operating, ambient temperature -20 110 c junction temperature 140 c storage temperature -65 150 c lead soldering temperature (10 seconds) 300 c
tmc2250a product specification rev. 1.0.2 10/25/00 17 operating conditions electrical characteristics notes: 1. except pins xc 11-0 , yc 11-8 . 2. pins xc 11-0 , yc 11-8 . parameter min nom max units v dd power supply voltage 4.75 5.0 5.25 v f clk clock frequency tmc2250a 30 mhz tmc2250a-2 40 mhz tmc2250a-3 50 mhz t pwh clk pulse width, high 6 ns t pwl clk pulse width, low 8 ns t s input data setup time 6 ns t h input data hold time 2 ns v ih input voltage, logic high 2.0 v v il input voltage, logic low 0.8 v i oh output current, logic high -2.0 ma i ol output current, logic low 4.0 ma t a ambient temperature, still air 0 70 c parameter conditions min typ max units i dd total power supply current v dd = max, c load = 25pf, f clk = max tmc2250a 125 ma tmc2250a-2 140 ma tmc2250a-3 155 ma i ddu power supply current, unloaded v dd = max, oe = high, f clk =max tmc2250a 120 ma tmc2250a-2 135 ma tmc2250a-3 150 ma i ddq power supply current, quiescent v dd = max, clk = low 12 ma c pin i/o pin capacitance 5 pf i ih input current, high 1 v dd = max, v in = v dd 5 a i il input current, low 1 v dd = max, v in = 0 v 5 a i ozh hi-z output leakage current, output high 2 v dd = max, v in = v dd 10 a i ozl hi-z output leakage current, output low 2 v dd = max, v in = 0 v 10 a i os short-circuit current -20 -80 ma v oh output voltage, high i oh = max, v dd = min 2.4 v v ol output voltage, low i ol = max, v dd = min 0.4 v
product specification tmc2250a 18 rev. 1.0.2 10/25/00 switching characteristics application notes performing large-kernel pixel interpolation the cascade input and output ports of the tmc2250a allow the user to stack multiple devices to perform larger interpolation kernels with no decrease in pixel throughput. figure 12 illustrates a basic application utilizing mode 11 to realize a 4 x 4-pi xel kernel, also called cubic convolution. this example utilizes the tmc2011a variable-length shift register to compensate for the internal latency of each tmc2250a. alternatively, some applications may utilize ram, fifo's, or other methods to store multiple-line pixel data. in these cases the user may compensate for latency by simply offsetting the access sequencing of the storage devices. figure 12. figure 12. performing cubic convolution with two tmc2250a's related products tmc2301 image resampling sequencer tmc2302a image manipulation sequencer tmc2249a video mixer tmc2242b half-band filter parameter conditions min typ max units t do output delay time c load = 25 pf 15 ns t ho output hold time c load = 25 pf 3 ns a 12 12 12 12 16 16 output b a b a b c d casout casout casin 4 x 2 tmc2250a 3 x tmc2111a 4 x 2 tmc2250a
tmc2250a product specification rev. 1.0.2 10/25/00 19 mechanical dimensions 120-lead cpga package d pin 1 identifier top view cavity up d1 p l a2 a b e b2 a1 a .080 .160 2.03 4.06 symbol inches min. max. min. max. millimeters notes a1 .040 .060 1.01 1.53 .215 5.46 a2 .125 3.17 b .016 .020 0.40 0.51 d 1.340 1.380 33.27 35.05 2 2 sq d1 .110 .145 2.79 3.68 e .050 nom. 1.27 nom. 1.200 bsc 30.48 bsc .100 bsc 2.54 bsc l l1 .170 .190 4.31 4.83 .003 .076 m13 13 120 120 3 4 n p b2 notes: 1. 2. 3. 4. 5. 6. pin #1 identifier shall be within shaded area shown. pin diameter excludes solder dip finish. dimension "m" defines matrix size. dimension "n" defines the maximum possible number of pins. orientation pin is at supplier's option. controlling dimension: inch.
product specification tmc2250a 20 rev. 1.0.2 10/25/00 mechanical dimensions 120-lead ppga package d pin 1 identifier top view cavity up d1 p l a2 a b e b2 a1 a .080 .160 2.03 4.06 symbol inches min. max. min. max. millimeters notes a1 .040 .060 1.01 1.53 .215 5.46 a2 .125 3.17 b .016 .020 0.40 0.51 d 1.340 1.380 33.27 35.05 2 2 sq d1 .110 .145 2.79 3.68 e .050 nom. 1.27 nom. 1.200 bsc 30.48 bsc .100 bsc 2.54 bsc l l1 .170 .190 4.31 4.83 .003 .076 m13 13 120 120 3 4 n p b2 notes: 1. 2. 3. 4. 5. 6. pin #1 identifier shall be within shaded area shown. pin diameter excludes solder dip finish. dimension "m" defines matrix size. dimension "n" defines the maximum possible number of pins. orientation pin is at supplier's option. controlling dimension: inch.
tmc2250a product specification rev. 1.0.2 10/25/00 21 mechanical dimensions 120-lead metric quad flat package to pin grid array package (mpga) d pin 1 identifier fairchild tmc2250a d1 a a2 l e b b2 a1 a3 e a .309 .311 7.85 7.90 symbol inches min. max. min. max. millimeters notes a1 .145 .155 3.68 3.94 .090 2.29 a2 a3 .080 2.03 b .016 .020 0.40 0.51 d 1.355 1.365 34.42 34.67 2 2 sq d1 .175 .185 4.45 4.70 e .050 nom. 1.27 nom. .050 typ. 1.27 typ. 1.200 bsc 30.48 bsc .100 bsc 2.54 bsc l m13 13 120 120 3 4 n b2 notes: 1. 2. 3. 4. 5. 6. pin #1 identifier shall be within shaded area shown. pin diameter excludes solder dip finish. dimension "m" defines matrix size. dimension "n" defines the maximum possible number of pins. orientation pin is at supplier's option. controlling dimension: inch.
product specification tmc2250a 22 rev. 1.0.2 10/25/00 mechanical dimensions 120-lead mqfp package d d1 e1 e e pin 1 identifier a2 a1 a b base plane seating plane see lead detail c 0 min. r 0.063" ref (1.60mm) lead detail l .20 (.008) min. .13 (.005) r min. -c- ccc c lead coplanarity notes: 1. 2. 3. 4. 5. all dimensions and tolerances conform to ansi y14.5m-1982. controlling dimension is millimeters. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "b" dimension. dambar cannot be located on the lower radius or the foot. "l" is the length of terminal for soldering to a substrate. "b" & "c" includes lead finish thickness. a .154 3.92 symbol inches min. max. min. max. millimeters notes a1 .010 .25 .018 .45 a2 .125 .144 3.17 3.67 b .012 3, 5 .30 .009 .23 c .005 .13 d1/e1 1.098 1.106 27.90 28.10 .0315 bsc .80 bsc e l .026 .037 .65 .95 120 120 30 30 4 5 n nd 0 7 0 7 .004 .10 ccc d/e 1.219 1.238 30.95 31.45 .13/.30 .005/.012
product specification tmc2250a life support policy fairchild s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 10/25/00 0.0m 002 stock#ds30002250a ? 2000 fairchild semiconductor corporation ordering information product number temperature range speed grade screening package package marking tmc2250ag1c 0 c to 70 c 30 mhz commercial 120 pin ceramic pin grid array 2250ag1c tmc2250ag1c2 0 c to 70 c 40 mhz commercial 120 pin ceramic pin grid array 2250ag1c2 tmc2250ag1c3 0 c to 70 c 50 mhz commercial 120 pin ceramic pin grid array 2250ag1c3 tmc2250ah5c 0 c to 70 c 30 mhz commercial 120 pin plastic pin grid array 2250ah5c tmc2250ah5c2 0 c to 70 c 40 mhz commercial 120 pin plastic pin grid array 2250ah5c2 tmc2250ah5c3 0 c to 70 c 50 mhz commercial 120 pin plastic pin grid array 2250ah5c3 tmc2250ah6c 0 c to 70 c 30 mhz commercial 120 lead metric quad flatpack to pin grid array n/a tmc2250ah6c2 0 c to 70 c 40 mhz commercial 120 lead metric quad flatpack to pin grid array n/a TMC2250AH6C3 0 c to 70 c 50 mhz commercial 120 lead metric quad flatpack to pin grid array n/a tmc2250akec 0 c to 70 c 30 mhz commercial 120 lead plastic quad flatpack 2250akec tmc2250akec2 0 c to 70 c 40 mhz commercial 120 lead plastic quad flatpack 2250akec2 tmc2250akec3 0 c to 70 c 50 mhz commercial 120 lead plastic quad flatpack 2250akec3

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